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The Write Through method called also by a write-through method assumes existence of two copies of data — one in the main memory, and another — in a cache memory. Each cycle of record of the processor goes to memory through a cache. It causes, of course, high loading of the system tire as two operations of record are the share of each operation of modification of data. Therefore each updating of contents a cache memory noticeably affects operation of the tire. On the other hand, the microprocessor is still compelled to expect the end of record in the main memory

When using the Write Back method called also by method of the return record, the cycle of record of the microprocessor occurs at first in a cache memory if there is a receiver address. If the receiver address in a cache memory does not appear, information registers directly in memory. Contents of the main memory are updated only when from a cache memory in it the full block of data called by length of a line cache (cache-line) registers

At data exchange there is a similar problem. Addresses of data which will soon be necessary for the processor for processing, are in most cases near addresses of the data processed directly at present. Therefore the cache controler has to care also of placement of all block of data in static memory

New chipset for processors of family 486, for example ALI M 1489 of firm, use some decisions developed for Pentium, in particular, possibility of use of memory like EDO DRAM, and also is supported by MISC processors of Cyrix and Enhanced 486 firm of AMD firm

The corresponding controler a cache memory has to care of that teams and data which will be necessary for the microprocessor at a given time, appeared in a cache memory by this moment. At some appeals to random access memory the corresponding values are brought in a cache. During the subsequent operations of reading on those to addresses of memory of the address occur only to a cache memory, without expense of processor time for expectation which is inevitable during the work with the main dynamic memory. In personal computers the technology of use a cache memory finds application first of all at data exchange between the microprocessor and random access memory, and also between the main memory and external (stores on magnetic carriers)

During the work about a cache memory the associative principle when the senior categories of the address are used as a sign, and younger — is applied to a word choice. The architecture a cache memory is defined by how memory is displayed on a cache. There are three kinds of display: a cache memory with direct display, partially associative and completely associative. At direct display each cell of the main memory can be displayed only on one cell of a cache, in the partially associative — on two and more (i.e. if one cell of a cache is occupied, it is possible to use another). In case of existence of four entrances a cache memory call 4-channel partially associative as, for example, at i48 At completely associative approach as categories of signs all address categories are used